
Job Description
Job Requirements
• Experience level 4-7 years
• Experience with micro-architecture and design of digital IPs and subsystems
• Understanding the RTL design and Uarch of IPs and integrating them in sub-systems
• SoC IP Uarch definition and RTL development
• Own RTL Quality Checks: Clock Domain Crossing (CDC) check, Lint, etc.
• Design for Testability (DFT) checks
• Low Power Checks
• RTL Synthesis and STA support
Work Experience
Experience with micro-architecture and design of digital IPs and subsystems
• Understanding the RTL design and Uarch of IPs and integrating them in sub-systems
• SoC IP Uarch definition and RTL development
• Own RTL Quality Checks: Clock Domain Crossing (CDC) check, Lint, etc.
• Design for Testability (DFT) checks
• Low Power Checks
• RTL Synthesis and STA support
Industries:Architecture & Planning, Computer Software, Mechanical Or Industrial Engineering
Job Skills
- RTL design
- DFT
- Software support
Job Overview
Date Posted
Location
Offered Salary
Not disclosed
Expiration date
Experience
